Hotfix SPB 16.30.022 (2011)

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Hotfix SPB 16.30.022 (2011)


Hotfix SPB 16.30.022 (2011) | 596 MB
Update for Cadence SPB/CAD 16.30.000 ... 16.30.021.
Revised Edition:
DATE: 01-14-2011 HOTFIX VERSION: 022
================================================== ================================================== ===============================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
================================================== ================================================== ===============================
372240 CAPTURE SCHEMATIC_EDITOR Allow component move with connectivity change should be checked by default
769139 SIP_LAYOUT DRC_CONSTRAINTS Wire to Bond finger rule in the CM needs profile to profile constraint capability
772299 ALLEGRO_EDITOR GRAPHICS Via doesn't get highlighted properly with OpenGL disabled
830519 ALLEGRO_EDITOR GRAPHICS Disabling openGL causes highlihting problems.
833981 RF_PCB FE_IFF_IMPORT DE HDL IMPORT IFF unit conversion and unit display in RF schematic
835698 RF_PCB FE_IFF_IMPORT DE HDL Import IFF to assign simple sig_names like RF001 RF002 etc
840094 RF_PCB OTHER dlibx2iff does not translate complex polygon pad
844504 SIG_EXPLORER INTERACTIV EMI Regulation setting of the board is not reflected correctly when the net is extracted into SigXP
846210 PDN_ANALYSIS PCB_STATICIRDROP IR Drop mesh is not correct.
846228 SIG_INTEGRITY OTHER ZAll and Wirebond calculation in the Prop Delay formula
846259 CONSTRAINT_MGR CONCEPT_HDL Why dont I see the P1_8V_DIG net in CM?
847278 CAPTURE TCL_INTERFACE TCL / TK PDF Export Change Page Size
847942 SIG_EXPLORER OTHER The solder resist layer was not included in Interconnect Model of SigXP.
848181 PSPICE DEHDL Model association for concept symbols with a chips view doesnt work
849707 ALLEGRO_EDITOR MANUFACT Thieving creates unwanted thermal reliefs in this design.
851070 CONSTRAINT_MGR CONCEPT_HDL The Match Groups are not visible in the CM
851171 F2B PACKAGERXL Design will not PACKAGE with exclude_cdsNotOnSym
851290 APD PADSTACK_EDITOR APD / SiP crashes when the user defined mask layer is edited with padeditdb.
851477 SPECCTRA ROUTE Allegro Router runs out of memory during route passes
851658 APD EDIT_ETCH bunceback behavior while slideing cline
851725 ALLEGRO_EDITOR DATABASE Number of DRC is not consistent on each DRC update.
851789 ALLEGRO_EDITOR SKILL Skill axlAirGap for Via and Text causes Allegro to crash
852325 ALLEGRO_EDITOR DATABASE Perf advisor doesn't check high pincount devices for RATSNEST_SCHEDULE
852360 SIG_INTEGRITY OTHER Appling toplogy template to a diff pair object reports UserDefined in CM
852395 ALLEGRO_EDITOR DRC_CONSTR Same net via spacing broken drc shows up to date
852764 ALLEGRO_EDITOR SKILL axlHttp beeps and gives error E - http 42
852787 CAPTURE ANNOTATE Tool is crashing during annotation if Ref Control is set
853110 ALLEGRO_EDITOR ARTWORK Allegro Crash on selecting Mfg> Artwork if any Parameter syntax is wrong in art_param.txt
854031 ALLEGRO_EDITOR MANUFACT The stream out data xxx.scf seems to be incorrect.
854246 ALLEGRO_EDITOR MANUFACT Stream out data of Oblong pad is strange.
854293 APD OTHER dynamic fillets were disappeared when open in 16.3.
854356 ALLEGRO_EDITOR OTHER Fillet adding doesn't check same net spacing rule in both static and dynamic mode.
855101 ALLEGRO_EDITOR OTHER Drill figures now smaller than expected
855124 APD PLOTTING The "load plot" command did not import Drill symbols (Figure) and Characters in APD.
855348 ALLEGRO_EDITOR EDIT_ETCH Differential Pairs do not slide to correct geometry
856220 ALLEGRO_EDITOR INTERFACES Export DXF in the 16.3 S021 build rotates some pin locations
856256 SIP_LAYOUT WIREBOND When editing a single Wirebond all wirebonds attached to the finger get highlighted.
856674 ALLEGRO_EDITOR AUTOVOID drill hole to shape autovoiding clearence is wrong for Same Net Spacing.
Year : 01/14/2011
Version: 16.30 Build 022
Developer: Cadence
Bit depth: 32bit
Compatibility with Vista: Unknown
Compatible with Windows 7: complete
System requirements:
Package installed Cadence SPB/CAD 16.30.0xx
Language: English

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